In the handling of semiconductor wafers in automated testing systems it is necessary to correctly position each wafer so that it can be passed from test station to test station with a known position and orientation. To establish that orientation, it is the practice in the art to perform an alignment on each wafer as taught in commonly assigned U.S. Pat. No. 4,457,664, Issued July 3, 1984.
Such an alignment involves detecting the edge positions of a wafer and repositioning it according to a predetermined alignment protocol. The edge is sensed by spinning the wafer over a capacitive sensitive edge detector, and misalignment and flat information is computer processed to identify the wafer movements necessary for it to be aligned according to the protocol.
As wafer processing technology becomes able to utilize wafers that might otherwise have failed to be acceptable for processing, it becomes necessary for the alignment system to deal with such wafers. One way that wafers can be less than perfect is to exhibit warp and bow distortions. These distortions can add an error term to the process of edge detection in the form of a displacement of the wafer not affecting the edge position, but affecting capacitance from the wafer. With such variations in displacement, come additional variations produced by the fringe field's complex dependence on the gap of the capacitive sensor.
Probes used to gauge semiconductor wafers in this environment are preferably small, stable, efficient to build and easy to adjust.